Intel Corporation
Load Balanced Decoder Systems And Methods

Abstract:

A decoding circuit system includes a load balancing scheduler circuit, a full range decoder circuit, and an auxiliary decoder circuit. The load balancing scheduler circuit provides codewords that each have a lifting factor greater than a predefined value to the full range decoder circuit. The full range decoder circuit decodes the codewords that each have a lifting factor greater than the predefined value to generate first decoded output data. The load balancing scheduler circuit provides codewords that each have a lifting factor less than the predefined value to the auxiliary decoder circuit. The auxiliary decoder circuit decodes the codewords that each have a lifting factor less than the predefined value to generate second decoded output data.