Intel Corporation
OPTIMIZATIONS OF BUFFER INVALIDATIONS TO REDUCE MEMORY MANAGEMENT PERFORMANCE OVERHEAD

Abstract:

Methods, apparatus, systems, and articles of manufacture to manage memory in a computing apparatus are disclosed. Methods, apparatus, systems, and articles of manufacture to optimize or improve buffer invalidation to reduce memory management performance overhead are disclosed. An example apparatus includes an input-output memory management unit (IOMMU) circuitry to control access to memory circuitry, the IOMMU circuitry to increment a counter from a first value to a second value when a memory access to a location in the memory circuitry is allocated and to decrement the counter from the second value to the first value when the memory access to the location in the memory circuitry is deallocated; and an operating system (OS) memory manager to enable reallocation of the location in the memory circuitry when the counter is at the first value.