Intel Corporation
Unified address space for multiple links

Abstract:

There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.