Intel Corporation
MULTI-RESET AND MULTI-CLOCK SYNCHRONIZER, AND SYNCHRONOUS MULTI-CYCLE RESET SYNCHRONIZATION CIRCUIT

Abstract:

An asynchronous multi-cycle reset synchronization circuit that can correlate any number of resets and synchronous clocks with simultaneous reset de-assertion and removal of reset assertion crossing hazards. The asynchronous multi-cycle reset synchronization circuit can also be paired with a synchronous multi-cycle reset synchronization circuit to correlate same domain asynchronous and synchronous resets. Also described is a synchronous reset multi-cycle synchronization circuit that correlates with any number of asynchronous resets and guarantees simultaneous reset de-assertion.