Intel Corporation
LOW POWER SEQUENTIAL CIRCUIT APPARATUS

Abstract:

A latch and/or flip-flop with reduced dynamic capacitance for the clock node. Power associated with the clock node is reduced without timing impact. Merely two clock devices and merely the signal on the clock input pin toggles when the data does not change. As such, power is reduced. Further, the latch is interrupted-based with no contention or jamming issues. The latch can be configured as master and slave latches to form a flip-flop.