Intel Corporation
Compressing error vectors for decoding logic to store compressed in a decoder memory used by the decoding logic

Abstract:

Provided are an apparatus, storage device, and method for compressing error vectors for decoding logic to store compressed in an decoder memory used by the decoding logic. A decoder decodes codewords to produce error vectors used to decode the codewords. A decoder memory device stores the error vectors. A compression unit receives the error vector from the decoder during decoding of the codeword. Each bit in the error vector has one of a first value and a second value. A determination is made of at least one bit location in the error vector having the first value. At least one pointer is stored in a row of memory cells in the decoder memory device indicating the determined at least one bit location in the codeword having the first value.