Intel Corporation
DUAL WRITE MICRO-OP QUEUE

Abstract:

Disclosed embodiments relate to systems and methods to dually write micro-ops to a micro-op queue. A processor includes a micro-op cache communicatively coupled, via a first write port, to a micro-op queue, and a legacy fetch and decode pipeline communicatively coupled, via a second write port, to the micro-op queue, the processor to determine whether the micro-op cache stores a thread, the thread comprising a micro-op to be written to the micro-op queue, determine whether the legacy fetch and decode pipeline stores the thread if the micro-op cache does not store the thread, and write, via the micro-op queue, the micro-op from the thread to the micro-op queue responsive to the determination of whether the micro-op cache or the legacy fetch and decode pipeline stores the thread.