Intel Corporation
MEMORY STRIPING APPROACH THAT INTERLEAVES SUB PROTECTED DATA WORDS

Abstract:

An apparatus is described. The apparatus includes a memory controller having logic circuitry to write a unit of write data into a plurality of memory chips according to a striping pattern that includes multiple protected sub words, each protected sub word including a smaller portion of the unit of write data and error correction coding (ECC) information calculated from the smaller portion of the unit of write data.