Intel Corporation
SELECTIVE INTERCONNECTS IN BACK-END-OF-LINE METALLIZATION STACKS OF INTEGRATED CIRCUITRY

Abstract:

An integrated circuit (IC) device structure, comprising a host chip having a device layer and one or more first metallization levels over adjacent first and second regions of the device layer. The first metallization levels are interconnected to the device layer. An interconnect chiplet is over the first metallization levels within the first region. The interconnect chiplet comprises a plurality of second metallization levels, and a plurality of third metallization levels over the first metallization levels within the second region and adjacent to the interconnect chiplet. At least one of an interconnect feature dimension or composition differs between one of the second metallization levels and an adjacent one of the third metallization levels.