Keysight Technologies, Inc.
Phase lock loops (PLLS) and methods of initializing PLLS

Abstract:

A phase lock loop (PLL) includes a phase detector configured to output a signal indicative of a phase difference between a reference signal and a feedback signal, a loop filter configured to filter an output of the phase detector, and a voltage-controlled oscillator (VCO) configured to output an oscillating signal having a frequency corresponding to an output of the loop filter. The PLL further includes a frequency divider configured to output the feedback signal by frequency dividing the oscillating signal output by the VCO, and a reset circuit configured to reset the frequency divider in an initialization mode such that a phase difference between the reference signal and the feedback signal corresponds to a lock angle of the PLL.