Keysight Technologies, Inc.
Methods, systems, and computer readable media for de-interleaving data in a communication system

Abstract:

A system includes a data bus, Q registers each having a register width B, and a receiver circuit. The receiver circuit is configured for receiving, at each clock cycle of a number of clock cycles of the communication system, a bit lane of data on a data bus, each bit lane including Q valid bits of an interleaved packet of length E. The receiver circuit is configured for placing, at each clock cycle, each of the Q valid bits into a respective bin of Q bins each having a bin width equal to the register width B. The receiver circuit is configured for determining that the bins are full, and in response to determining that the bins are full, transferring the contents of the bins into the registers.