Everspin Technologies, Inc.
ECC word configuration for system-level ECC compatibility

Abstract:

A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page, such that a first level of error correction is performed by the memory device on each of the ECC words associated with a page, and a second level of error correction is performed on the data output by each of the input/output pads, during a particular period of time. Each of the one or more input/output pads of the memory device is configured to provide only one bit of data per ECC word to an external source during an access from the external source.