Micron Technology, Inc.
Write buffer implementation for multiple memory array memory spaces

Abstract:

A memory device comprises a memory array including memory cells programmable as single level memory cells (SLCs) and memory cells programmable as triple level memory cells (TLCs); a memory control unit operatively coupled to the memory array and including a processor, the processor configured to program the memory cells with SLC data and TLC data; and a write buffer to buffer data for writing to the memory array, the write buffer including both SLC data memory space and TLC data memory space, wherein the memory control unit is configured to store TLC data in the SLC data memory space when there is overflow of the TLC data memory space.