Micron Technology, Inc.
Arbiter circuit for commands from multiple physical functions in a memory sub-system

Abstract:

A system controller of a memory system can present multiple physical functions (PFs) to a host computing system. The system controller can store commands from the host in separate queues and uses an arbiter circuit to issue commands. The arbiter can determine a difference value between a quota of commands and a count of commands issued from a respective queue. The quota is derived from a share specified by the host for the respective PF. The arbiter circuit determines a subset of queues by excluding queues that are empty and queues having a negative difference value. The arbiter circuit can randomly choose a selected queue from the subset and issue a command from the selected queue.