Micron Technology, Inc.
MULTIPLE PIN CONFIGURATIONS OF MEMORY DEVICES

Abstract:

An apparatus configured to allow data values to be written into the plurality of memory cells of the memory device at a first speed upon connecting to a first host via a first configuration of the plurality of connectors; and allow data values to be written into the plurality of memory cells at a second speed faster than the first speed, upon connecting to a second host via a second configuration of the plurality of connectors.