Micron Technology, Inc.
Memory device error detection with improved scanning

Abstract:

A memory device may include memory cells configured to establish multiple levels of charge distributions; and a memory controller configured to perform operations on the memory cells. The operations may include recording a bit count number for a highest level of charge distributions within a set of memory cells, recording a bit count number for a lowest level of charge distributions within the set of memory cells, counting bits for the highest level of charge distributions within the set of memory cells, counting bits in the lowest level of charge distributions within the set of memory cells, comparing the counted bits for the highest level to the recorded bit count number for the highest level, and comparing the counted bits for the lowest level to the recorded bit count number for the lowest level.