Micron Technology, Inc.
A MEMORY DEVICE ARCHITECTURE COUPLED TO A SYSTEM-ON-CHIP

Abstract:

The present disclosure relates to a Flash memory portion architecture coupled to a System-on-Chip (SoC) including a matrix of memory cells with associated decoding and sensing circuitry and having a structurally independent structure linked to the System-on-Chip and comprising: a plurality of sub arrays forming the matrix of memory cells; sense amplifiers coupled to a corresponding sub array; a data buffer including a plurality of JTAG cells coupled to the outputs of the sense amplifiers;