Micron Technology, Inc.
JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION

Abstract:

The present disclosure relates to an apparatus comprising: a memory component having an independent structure and including at least an array of memory cells with associated decoding and sensing circuitry and a memory controller; a host device including multiple cores and coupled to the memory component through at least a communication channel for each corresponding core; a control and JTAG interface in said at least an array of memory cells; at least an additional register in said control and JTAG interface for handing data, addresses and control signals provided by the host device and to be delivered to said decoding circuitry and to said controller to perform modify operations.