Micron Technology, Inc.
ACCELERATION CIRCUITRY FOR POSIT OPERATIONS

Abstract:

Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. A first operand formatted in a universal number or posit format can be received by a first buffer resident on acceleration circuitry. A second operand formatted in a universal number or posit format can be received by a second buffer resident on the acceleration circuitry. An arithmetic operation, a logical operation, or both can be performed using processing circuitry resident on the acceleration circuitry using the first operand and the second operand. A result of the arithmetic operation, the logical operation, or both can be received by a third buffer resident on the acceleration circuitry.