Micron Technology, Inc.
Managing memory commands in a memory subsystem by adjusting a maximum number of low priority commands in a DRAM controller

Abstract:

A method is described for managing issuance of memory commands. The method includes determining whether a number of high priority commands from a cache controller meets a first threshold. In response to meeting the first threshold, a second threshold, which indicates a maximum number of low priority commands allowed in a low latency memory command queue, is set to a first value. In response to not meeting the first threshold, the second threshold is set to a second value. The method further selects a memory command for issuance from the cache controller command queue, wherein the memory command is a high priority memory command when the number of low priority memory commands stored in the low latency memory controller command queue meets the second threshold and is a low priority memory command when the number of low priority memory commands does not meet the second threshold.