Micron Technology, Inc.
Cache release command for cache reads in a memory sub-system

Abstract:

A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a first cache read command requesting first data from the memory array spread across the plurality of memory planes, and returns, to the requestor, data associated with a first subset of the plurality of memory planes and pertaining to a previous read command, while concurrently copying data associated with a second subset of the plurality of memory planes and pertaining to the previous read command into the cache register. The control logic further receives, from the requestor, a cache release command, and returns, to the requestor, the data associated with the second subset of the plurality of memory planes and pertaining to the previous read command, while concurrently copying data associated with the first subset of the plurality of memory planes and pertaining to the first cache read command into the cache register.