Micron Technology, Inc.
Memory sub-system with multiple ports having single root virtualization

Abstract:

A processing device to perform operations including detecting a first host system connected to a first interface port of the plurality of interface ports of the memory device, the first host system is one of a plurality of host systems. Detecting a second host system connected to a second interface port of the plurality of interface ports, the second host system is one of the plurality of host systems. Assigning a first subset of a plurality of virtual functions (VF)s associated with the memory device to the first host system using root input/output virtualization (SR-IOV) and assigning a second subset of the plurality of VFs to the second host system using SR-IOV. Allocating a first corresponding range of logical block addresses (LBA) to each VF of the first subset of VFs and allocating a second corresponding range of LBAs to each VF of the second subset of VFs.