Micron Technology, Inc.
Staggered refresh counters for a memory device

Abstract:

Methods, systems, and devices for staggered refresh counters for a memory device are described. The memory device may include a set of memory dies each coupled with a common command and address (CA) bus and each including a respective refresh counter. In response to a refresh command received over the CA bus, each memory die may refresh a set of memory cells based on a value output by the respective refresh counter for the memory die. The refresh counters for at least two of the memory dies of the memory device may be offset such that they indicate different values when a refresh command is received over the CA bus, and thus at least two of the memory dies may refresh memory cells in different sections of their respective arrays. Offsets between refresh counters may be based on different fuse settings associated with the different memory dies.