Micron Technology, Inc.
Noise reduction during parallel plane access in a multi-plane memory device

Abstract:

A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to track a status of the plurality of independent plane driver circuits and detect an occurrence of a quiet event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits. The control logic is further to determine whether a high noise event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring. Responsive to determining that the high noise event associated with the second independent plane driver circuit is concurrently occurring, the control logic is to determine whether the first independent plane driver circuit has a higher priority than the second independent plane driver circuit. Responsive to determining that the first independent plane driver circuit has a higher priority than the second independent plane driver circuit, the control logic is to suspend the high noise event associated with the second independent plane driver circuit and permitting the quiet event associated with the first independent plane driver circuit to occur.