Micron Technology, Inc.
DISTRIBUTED INFERENCING USING DEEP LEARNING ACCELERATORS WITH INTEGRATED RANDOM ACCESS MEMORY

Abstract:

Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory. At least one interface of the integrated circuit device is configured to receive input data from a data source, and to receive, from a server system over a computer network, parameters of a first Artificial Neural Network (ANN) and instructions executable by the Deep Learning Accelerator to perform matrix computation of the first ANN. The Deep Learning Accelerator may execute the instructions to generate an output of the first ANN responsive to the third data; and the at least one interface is configured to transmit the output to the server system over the computer network as an input to a second ANN in the server system.