Micron Technology, Inc.
LOCALIZED MEMORY TRAFFIC CONTROL FOR HIGH-SPEED MEMORY DEVICES

Abstract:

A processing device receives a series of commands associated with a memory device. The memory device includes memory cells that are distributed among multiple planes. The processing device identifies a respective plane to which each command is directed, and places a respective set of commands directed to the respective plane in a corresponding queue associated with the respective plane. A first set of commands placed in a first queue associated with a first plane are processed first. Responsive to determining that a predetermined criterion is satisfied, a second set of commands placed in a second queue associated with a second plane are processed. To minimize having to switch between different planes while responding to read/write commands, wear-leveling is restricted to each plane using overprovisioning capacity in each plane.