Micron Technology, Inc.
SYSTEMS AND METHODS FOR USING COLUMN REDUNDANCY FOR ERROR BIT DETECTION AND CORRECTION

Abstract:

Memory devices may include circuitry to prevent erratic behavior of defective memory cells by detecting and storing a location of defective memory cells in designated Column Redundancy (CR) arrays. Memory devices may also use an Error Correction Code (ECC) scheme to store ECC information for detection and correction of a number of erroneous data bits stored on the memory cells. The ECC information may provide information related to integrity of the data bits of the data array with no regard to possible erratic behavior of memory cells. However, corruption of a data bit is likely to be caused by an erratic behavior of defective memory cells. As such, systems and method for storing a location of one or more erroneous data bits of a dataset obtained using ECC information for reuse. In some embodiments, the memory may store and access such location information using the designated memory cells of one or more CR arrays to correct at least an extra erroneous data bit in a later memory operation.