Micron Technology, Inc.
TWO-STAGE HYBRID MEMORY BUFFER FOR MULTIPLE STREAMS

Abstract:

Described herein is a system comprising one or more external dynamic random access memory (DRAM) devices having a first programming unit buffer and a second programming unit buffer, an internal static RAM (SRAM) device, one or more non-volatile memory (NVM) devices, and a processing device, operatively coupled with the one or more external DRAM devices, the internal SRAM device, and the one or more NVM devices. The processing device transfers first write data from the first programming unit buffer to the internal SRAM device responsive to the first write data satisfying a programming unit (PU) threshold, the PU threshold pertaining to a PU of the one or more NVM devices. The processing device also writes the first write data from the internal SRAM device as a first programming unit to the one or more NVM devices, and transfers a second write data from the second programming unit buffer to the internal SRAM device responsive to the second write data satisfying the PU threshold. The processing device further writes the second write data from the internal SRAM device as a second programming unit to the one or more NVM devices.