Micron Technology, Inc.
Power disable of memory sub-system

Abstract:

A system includes a memory device and a power disable circuit coupled to a bus connector and to power circuitry adapted to power on and off the memory device. A processing device is coupled to the bus connector, to the power disable circuit, and to the memory device. The processing device is to monitor a state of a power disable (PWDIS) signal of the bus connector while the PWDIS signal is at a first voltage level, and in response to the PWDIS signal transitioning to a second voltage level, determine whether a length of time for which the PWDIS signal has been at the second voltage level satisfies a threshold criterion. In response to the length of time for which the PWDIS signal has been at the second voltage level satisfying the threshold criterion, the processing device is to enable the power disable circuit with a general purpose input/output signal.