Micron Technology, Inc.
THREAD EXECUTION CONTROL IN A BARREL PROCESSOR

Abstract:

Devices and techniques for thread execution control in a barrel processor are described herein. An apparatus includes a barrel processor, which includes local memory including a hazard data structure; and thread scheduling circuitry; wherein the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including: identifying an instruction to place into a pipeline for the barrel processor, the instruction corresponding to a thread; reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a preceding instruction in the thread; and in response to reading the hazard indication entry, rescheduling the thread to a later time based on the hazard identification.