Micron Technology, Inc.
MEMORY BUS DRIVE DEFECT DETECTION

Abstract:

Methods, systems, and devices for memory bus drive defect detection and related operations are described. A controller coupled with a memory array may receive a command for data. The memory array may include one or more pins for communicating data to and from the memory array, in response to the command. The controller may transmit to the memory array, over a bus that is coupled with the controller and the pins, the command. The controller may detect, based at least in part on a resistor coupled with the bus and a power supply of the memory array, that the bus is operating in a first state after transmitting the command. The first state may comprise a voltage that is relatively higher than a voltage of the second state. The controller may determine a defect associated with the bus or the pin based on detecting the bus in the first state.