Micron Technology, Inc.
Dynamic program erase targeting with bit error rate

Abstract:

A system includes a memory array with memory cells and a processing device coupled thereto. The processing device performs program targeting operations that include to: determine a set of difference error counts corresponding to programming distributions of the memory array; identify, based on a comparison of the set of difference error counts, valley margins corresponding to the programming distributions; select, based on values of the valley margins, a program targeting rule from a set of rules; perform, based on the program targeting rule, a program targeting operation to adjust a voltage level associated with an erase distribution of the memory array; determine a bit error rate (BER) of the memory array; in response to the BER satisfying a BER control value, reduce the voltage level by a voltage step; and in response to the BER not satisfying the BER control value, increase the voltage level by the voltage step.