Micron Technology, Inc.
LOW-BIT DENSITY MEMORY CACHING OF PARALLEL INDEPENDENT THREADS

Abstract:

A first data item is programmed to a first memory page of a first block included in a cache that resides in a first portion of a memory device. The first data item is associated with a first processing thread. A second memory page including a second data item associated with the first processing thread is identified. The second memory page is contained by a second block of the cache. The first data item and the second data item are copied to a second portion of the memory device. The first memory page and each of the one or more second memory pages are designated as invalid.