Micron Technology, Inc.
ACCELERATED READ TRANSLATION PATH IN MEMORY SUB-SYSTEM

Abstract:

A system includes a non-volatile memory device and a processing device to perform operations including creating a logical transfer unit (LTU) corresponding to a logical block address (LBA) received in a read request, wherein the LTU comprises a subset of a plurality of sequential LBAs of a zone of LBA space of the non-volatile memory device, wherein one of the subset is the LBA. The processing device comprises a hardware accelerator to perform operations comprising: retrieving, using an LTU identifier associated with the LTU, metadata that specifies a mapping between the LTU identifier and a physical address of a physical address space; and providing the metadata for use in determining and utilizing the physical address to perform a read operation specified by the read request.