Micron Technology, Inc.
Payload parity protection for a synchronous interface

Abstract:

A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A controller or primary device coupled to the SPI bus can generate a message with read or write instructions for one or more secondary devices. In an example, the primary device can be configured to read information from a secondary device about whether the secondary device supports parity-protected data communications. The primary device can be configured to selectively send or receive parity-protected data communications depending on a capability of the secondary device to support parity.