Micron Technology, Inc.
Independent parallel plane access in a multi-plane memory device

Abstract:

A memory device includes a memory array comprising a first number of planes, a second number of independent plane driver circuits, wherein the second number is less than the first number, and a plane selection circuit to couple the second number of independent plane driver circuits to the first number of planes of the memory array. The memory device further includes control logic, to perform receive a first read command and identify, among the first number of planes, a first plane to which the first read command is directed. The control logic further configures the plane selection circuit to couple a first independent plane driver of the second number of independent plane drivers to the first plane and causes the first independent plane driver to perform a first read operation corresponding to the first read command on the first plane.