Micron Technology, Inc.
Semiconductor memory device capable of performing soft-post-package-repair operation

Abstract:

Disclosed herein is an apparatus that includes a first address generator generating a first address in response to a clock signal; a second address generator generating a second address corresponding to the first address; a first detection circuit activating a first signal when the second address matches with a third address; a second detection circuit activating a second signal when the second address indicates a predetermined state; a first latch circuit latching the first address in response to the first signal; a second latch circuit latching the first address in response to the second signal; a third detection circuit activating a third signal when the first address matches with an address stored in the first latch circuit; a fourth detection circuit activating a fourth signal when the first address matches with an address stored in the second latch circuit; and a first selector selecting the third or fourth signal.