Micron Technology, Inc.
Sequential write and sequential write verify in memory device

Last updated:

Abstract:

Some embodiments include apparatuses and methods for performing a first stage of an operation of storing information in a first memory cell and a second memory cell, and performing a second stage of the operation after the first stage to determine whether each of the first and second memory cells reaches a target state. The first memory cell is included in a first memory cell string coupled to a data line through a first select transistor. The second memory cell is included in a second memory cell string coupled to the data line through a second select transistor.

Status:
Grant
Type:

Utility

Filling date:

22 Jul 2019

Issue date:

25 May 2021