Micron Technology, Inc.
Erasing memory cells

Abstract:

Apparatus including an array of memory cells comprising a plurality of strings of series-connected memory cells, a plurality of access lines each connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of series-connected memory cells, and a controller configured during an erase operation of the plurality of strings of series-connected memory cells to apply a first voltage level to a node connected to an end of a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells, and apply a second voltage level to a particular access line of the plurality of access lines concurrently with applying the first voltage level to the node, wherein the second voltage level has a magnitude greater than the first voltage level, and is lower than the first voltage level.