Micron Technology, Inc.
Preemptive read refresh in memories with time-varying error rates

Abstract:

A processing device in a memory sub-system receives a read request from a host system, the read request identifying data stored in a segment of a memory component, and performs a first read operation on the segment using a first read voltage level. The processing device determines whether the data read during the first read operation was successfully decoded. If so, the processing device determines a write-to-read (W2R) delay time for the segment and determines whether the W2R delay time within a first W2R delay range, wherein the first W2R delay range represents a first plurality of W2R delay times corresponding to the first read voltage level. Responsive to the W2R delay time for the segment not falling within the first W2R delay range, the processing device performs a read refresh operation on at least a portion of the segment using an applicable read voltage level.