Micron Technology, Inc.
Quality of service levels for a direct memory access engine in a memory sub-system

Abstract:

A processing device, operatively coupled with a plurality of memory devices, is configured to receive a direct memory access (DMA) command for moving a plurality of data sectors from a source memory region to a destination memory region, the DMA command comprising a priority value. The processing device further assigns the DMA command to a priority queue of a plurality of priority queues based on the priority value of the DMA command, each priority queue has a corresponding set of priority values. The processing device also determines an execution rate for each priority queue of the plurality of priority queues. The processing device then executes a plurality of DMA commands from the plurality of priority queues according to the corresponding execution rate of each priority queue.