Micron Technology, Inc.
DETAILED FAILURE NOTIFICATIONS IN MEMORY SUB-SYSTEMS

Abstract:

Disclosed is a system comprising a memory component and a processing device operatively coupled with the memory component, to provide, to a host system, geometric parameters of the memory component, receive, from the host system, a first data to be stored in the memory component, execute a first write operation to program the first data into the memory component, detect that the first write operation has failed, provide a failure notification to the host system, wherein the failure notification comprises an indication of a range of memory cells storing, after the first write operation, incorrect data, and receive, from the host system, a second data to be stored in the memory component, in response to the host system identifying, based on the geometric parameters and the failure notification, a range of logical addresses of the memory component corresponding to the range of memory cells storing incorrect data