Micron Technology, Inc.
NAND DEVICE MIXED PARITY MANAGEMENT

Abstract:

Devices and techniques for NAND device mixed parity management are described herein. A first portion of data that corresponds to a first data segment and a second data segment--respectively defined with respect to a structure of a NAND device--are received. A parity value using the first portion of data and the second portion of data is computed and then stored for error correction operations.