Nordic Semiconductor ASA
Decoder for low-density parity-check codes

Abstract:

Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is P.sub.CNB (where P.gtoreq.P.sub.CNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than P.sub.CNB*q bits.