Nutanix, Inc.
HARDWARE-ASSISTED PAGE ACCESS TRACKING

Abstract:

A memory subsystem is interfaced to a CPU through memory controllers. The memory subsystem is composed of a first tier of first memory devices having a first set of performance characteristics and a second tier of second memory devices having a second set of performance characteristics that are different from the first set of performance characteristics. A content addressable memory stores the memory addresses that are used to access the first memory devices and/or second memory devices. Logic is provided that updates one or more registers or memory structures to count the frequency and timing of occurrences of the memory address accesses. Both the content addressable memory and logic can be implemented on the same semiconductor substrate. The content addressable memory may be interfaced to a random access memory that stores counters. The logic may comprise one or more state machines implemented on the same semiconductor substrate as the CPU.