QUALCOMM Incorporated
Multiple via structure for high performance standard cells

Abstract:

A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first M.sub.x layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second M.sub.x layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second M.sub.x layer interconnects are parallel. The MOS device further includes a first M.sub.x+1 layer interconnect extending in a second direction orthogonal to the first direction. The first M.sub.x+1 layer interconnect is coupled to the first M.sub.x layer interconnect and the second M.sub.x layer interconnect. The MOS device further includes a second M.sub.x+1 layer interconnect extending in the second direction. The second M.sub.x+1 layer interconnect is coupled to the first M.sub.x layer interconnect and the second M.sub.x layer interconnect. The second M.sub.x+1 layer interconnect is parallel to the first M.sub.x+1 layer interconnect.