QUALCOMM Incorporated
VERTICAL POWER GRID STANDARD CELL ARCHITECTURE

Abstract:

A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every m.sup.th track, where 2.ltoreq.m<P.sub.PG and P.sub.PG is a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell. The first set of PG Mx layer interconnects have the pitch P.sub.PG>m*P