QUALCOMM Incorporated
VIA ZERO INTERCONNECT LAYER METAL RESISTOR INTEGRATION

Abstract:

An integrated circuit (IC) is described. The IC includes a substrate having an active device having an active region. The IC also includes a middle-of-line (MOL) interconnect layer having a contact merge (CM) layer on a trench contact coupled to the active region of the active device. The IC further includes back-end-of-line (BEOL) interconnect layers on the MOL interconnect layer. The IC also includes a metal resistor in a via zero interconnect layer between a first BEOL interconnect and the MOL interconnect layer. The metal resistor is coupled to the active region through a first via zero on the CM layer, a second via zero on the metal resistor, and the first BEOL interconnect on the first via zero and the second via zero.