QUALCOMM Incorporated
Delay locked loop with segmented delay circuit

Abstract:

A system includes delay locked loop (DLL) including a phase detector having a first input coupled to an input of the DLL, and a first delay circuit and a second delay circuit coupled in series between the input of the DLL and a second input of the phase detector. The DLL further includes a first control circuit, wherein an input of the first control circuit is coupled to an output of the phase detector, a first output of the first control circuit is coupled to a control input of the first delay circuit, and a second output of the first control circuit is coupled to a control input of the second delay circuit. The system also includes a second control circuit having an input coupled to the first control circuit, and a slave delay circuit having a control input coupled to an output of the second control circuit.