QUALCOMM Incorporated
Multibit multi-height cell to improve pin accessibility

Abstract:

A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of M.sub.x layer interconnects on an M.sub.x layer extending in a first direction over the first and second subcells. A first subset of the first set of M.sub.x layer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of M.sub.x layer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.